To achieve faster operating speeds, integrated circuits (IC's) are being developed with smaller feature sizes and higher densities of components. Conductivity of metal interconnections has emerged as a limitation in the development of these high performance devices. Thus, future generations of IC's will tend to substitute copper for the presently used aluminum conductors.
Forming electrically conducting vias, contacts, and conductors of copper or other metals becomes increasingly challenging as feature sizes are reduced. Techniques for forming such metal features include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD) and electrochemical deposition (also referred to as electroplating or electrodeposition.)
The general nature of the electroplating process is well known. The wafer is immersed in an electrolytic bath containing metal ions and is biased as the cathode in an electric circuit. With the solution biased positively, the metal ions become current carriers which flow towards and are deposited on the exposed surfaces of the wafer. Electroplating is particularly well suited for the formation of small embedded damascene metal features due to the ability to control (at least in part) the growth of the electroplated film for bottom-up filling and due to the superior electrical conductivity characteristics of the electroplated film. However, there are also several obstacles that need to be overcome in order to realize these advantages fully.
One challenge facing damascene processing techniques is the difficulty of initiating the growth of the metal film within recessed features without forming voids or seams. In typical PVD and some CVD processes, metal may preferentially deposit near the top of recessed features leading to a “bottleneck” shape. Further plating of metal onto the bottleneck may result in sealing the top of the feature before completely filling the feature with metal, creating a void. Voids increase the resistance of the conductor over its designed value due to the absence of the planned-for conductor. Also, trapped electrolyte in sealed voids may corrode the metal. This may lead to degraded device performance or device failure in extreme cases.
Maintaining a smooth copper surface can be particularly challenging during the initial phases of electroplating, as shown in FIGS. 1A through 1F, which are atomic force microscopy (“AFM”) images of an electroplated copper layer at increasing thicknesses. FIG. 1A illustrates the smooth seed layer, having a roughness of only 1.68 root mean square (“RMS”), which is a basis of comparison often used in defining surface roughness determined by AFM measurements. After only 140 Å of copper are deposited, the roughness is almost 4 times greater (FIG. 1B). By the time the copper layer reaches 1300 Å in thickness, the roughness has increased to 12.3 RMS (FIG. 1C). As shown in FIGS. 1D through 1F, this roughness tends to decrease as the copper layer grows.
Current technology electroplating baths typically contain three organic additive components in addition to the bulk electrolyte solution. These additives are typically referred to as accelerators, suppressors, and levelers. The combination of accelerator and suppressor in the presence of chloride ions, produces the bottom-up fill effect which allows for filling of recessed trenches and vias. As a result of the accelerated growth within small features, a region of thicker copper exists over the features after plating, commonly referred to as overplating, due to accelerator additives locally concentrated on the copper surface after filling. A high level of overplating can result in CMP dishing or overpolish problems. The leveler additive acts to displace the accumulated accelerator molecule above features, reducing the rate of accelerated growth and thus reducing the overplating, which in turn improve CMP process performance. However, due to the fact that leveler molecules act to displace accelerator molecules, they have a strong impact on the bottom-up fill process when present in high concentration. If the leveler molecule displaces or inhibits adsorption of accelerator molecule prior to fill completion, voids or seams will occur. Therefore, in current electrofill process technology, there exists a trade-off in the leveler concentration in the bath between void-free trench fill at low leveler concentrations and overplating reduction at high leveler concentrations.
Overplating reduction approaches include the use of large slowly diffusing leveling additives and mass transfer conditions which limit leveler diffusion into features, application of reverse currents to displace accelerating additives from the copper surface following the completion of superfilling, plating sequentially in superfilling and highly leveling baths, leveling additives which accumulate on the copper surface and gradually increase leveling activity after superfilling of small features is complete, and relevant to this patent application, pretreatment with accelerator additives followed by plating in high leveling baths. The goal of each of these processes is to maintain the initial very rapid bottom-up plating essential to void-free filling, but to halt the accelerated deposition process over dense features once the filling process is completed.
What is needed is an electroplating technique that produces metal films and features without voids or defects, particularly during the initial phases of the electroplating process, as well as a process that produces a high rate of bottom-up fill within features followed by rapid leveling of the plated copper film.